ANSYS Totem

Industry-proven and foundry-certified analog and mixed-signal EM/IR solution

ANSYS Totem is a transistor-level power noise and reliability analysis platform that enables you to perform comprehensive power integrity analysis on analog mixed-signal IP and full custom designs.

Totem enables creation of IP models for SOC-level power integrity signoff using RedHawk and generates compact chip models of power delivery networks for a variety of analyses including power integrity and ESD/EMC at chip and system-level.

Redefining Analog/Mixed Signal Signoff

	Traditional Power-Noise-Reliability Analysis Flows	ANSYS Totem Based Re-defined Full-Chip Signoff Flows
MIXED SIGNAL DESIGN PROTOTYPING	No Analysis Available at early stages Need a clean GDS/Netlist	Grid Prototyping Analysis GDS Only flows for early stage weakness checks
LAYOUT VERIFICATION	Need detailed PG extracted net-list Fast spice simulators chokes for even medium sized designs	Totem extracts PG grid itself, capacity to handle ultra large designs Several Million Xtor FLAT Analysis capacity
METAL FIXES & ECO	Complete re-run of the flow from LVS to simulation needs to be performed which may take several days Multiple iterations are very hard to accomplish before Tape-in No What-if capabilities	Incremental analysis with new GDS can be run, which is few minutes to hours Abundant what-if scenarios and study possible to make intelligent fixes
FULL CHIP INTEGRATION	Combining Digital + Analog not possible	Totem can simultaneously handle Digital (P&R) blocks + Analog (Full Custom) blocks in one single simulation

Totem delivers:

Best-in-Class Signoff Analysis

Totem’s core engines for extraction, simulation, electromigration and self-heat analysis are certified for all major technology nodes and correlated several times against spice and silicon measurements. Totem is certified across several major foundries and is the preferred signoff tool for several major semiconductor companies.

The Only Complete Solution

Totem supports all major data formats (GDS, OASIS, LVS database, etc.) for analog, LEF/DEF (for digital) and is compatible with all major spice simulation environments. It has capacity to handle very large designs and possesses superior macro-modeling capabilities for generating an accurate and compact IP model for SOC signoff.

Broad Design Coverage

Totem provides a comprehensive suite of analyses spanning early stage to signoff. It can effectively handle a variety of design styles such as SerDes, data converters, power management IC, embedded memories, DRAM, Flash, FPGA and chip image sensors. Additionally, it delivers numerous analysis capabilities including substrate noise analysis, RDSON analysis, thermal and ESD analysis to address challenges in different designs. It also provides a configurable cockpit for customers to customize their analysis based on their workflows.